1. Field of the Invention
This invention relates to a semiconductor memory device, and particularly to a ferroelectric memory device and operation method therefor.
2. Description of Related Art
Conventionally, in semiconductor memory devices, there is well known the so-called DRAM (dynamic memory) wherein electrical charges are stored in capacitors formed internally therein, and wherein data are stored according to the presence or absence of such charges. In recent years, devices wherein ferroelectric films are used as insulative films in such capacitors are being given much attention with respect to their high level of integration, high speed, and low power consumption.
One example of a ferroelectric memory device is disclosed in Reference 1 (T. Sumi et al.: xe2x80x9cA 256 kb Nonvolatile Ferroelectric Memory at 3 V and 100 ns,xe2x80x9d ISSCC Digest of Technical Papers, P 268-269 (February, 1994).xe2x80x9d FIG. 11 schematically shows the configuration of the ferroelectric memory device described in Reference 1.
In FIG. 11, one memory cell 508 is representatively diagrammed. In actual practice, however, this kind of memory cell is arranged in a matrix array to form a memory cell array 520.
In the device shown in FIG. 11, a 2T2C type memory cell 508 is configured by two ferroelectric capacitors 500 and 502 and two MOSFETs 504 and 506. The ferroelectric capacitor 500 is connected in series with the MOSFET 504. Similarly, the ferroelectric capacitor 502 is connected in series with the MOSFET 506. The terminals of the ferroelectric capacitors 500 and 502 the are not connected to the MOSFETs 504 and 506 are connected, respectively, to a plate line 510. The MOSFET gates 504x and 506x are connected, respectively, to a word line 512. The terminal of the MOSFET 504 the is not connected to the ferroelectric capacitor 500 is connected to a bit line 514. Similarly, the terminal of the MOSFET 506 the is not connected to the ferroelectric capacitor 502 is connected to a complementary bit line 516. A memory cell array 520 is configured containing the memory cell 508, plate line 510, word line 512, bit line 514, and complementary bit line 516. Both the bit line 514 and the complementary bit line 516 are connected to a common sense amplifier 518. In this device, moreover, a word driver 522 the makes the word line 512 either active (logic level xe2x80x9c1xe2x80x9d state) or inactive (logic level xe2x80x9c0xe2x80x9d state) is connected to each word line 512. To the word drivers 522 are connected a row decoder 524 the provides signals for instructing each word driver 522 to operate. To each of the row decoders 524 are applied a row address selection signal (RAdd) and a row decoder energize signal (RAE). When both of these signals are applied to as row decoder 524, the row decoder 524 connected to a specific word line, such as word line 512, for example, is selected to provide a prescribed potential level. To each plate line 510, moreover, is connected a plate driver 526 that puts the plate line 510 at a prescribed potential level. Each plate driver 526 is connected to a word line 512 and when the word line 512 becomes active, a signal that originates in the word line 512 is applied to the plate driver 526. To the plate driver 526 is also applied a control signal (RS) for controlling the operation timing wherewith rows are selected. The plate driver 526, moreover, produces an output corresponding to logic level xe2x80x9c1xe2x80x9d only when both the control signal (RS) and the signal originating in the word line 512 are applied thereto.
With reference to FIG. 11 and FIG. 12, the operation of reading data out from the ferroelectric memory device shown in FIG. 11 will hereinafter be described. FIG. 12 shows a timing chart for explaining data read operations in the conventional ferroelectric memory device described above. In FIG. 12, the symbol xe2x80x9cLxe2x80x9d represents a binary xe2x80x9c0xe2x80x9d (corresponding to logic level xe2x80x9c0xe2x80x9d), such as the level at ground potential, while the symbol xe2x80x9cHxe2x80x9d represents a binary xe2x80x9c1xe2x80x9d (corresponding to logic level xe2x80x9c1xe2x80x9d), such as the level at the power supply potential. In FIG. 12(F), the potential changes (BL, /BL) of the bit line 514 and complementary bit line 516 are represented, respectively. Here, because the timing wherewith the low decoder energize (or activation) signal (RAE) is applied and the timing wherewith the row address selection signal (RAdd) is applied to the row decoder 524 are substantially coincident, the timing of the application of both of these signals is represented by a common continuous line in FIG. 12(A). FIG. 12(B) shows the timing wherewith the control signal (RS) is applied to the plate line 510, FIG. 12(C) the timing (WL) wherewith the word line 512 becomes either active or inactive, FIG. 12(D) the timing (PL) wherewith the plate line 510 becomes either active or inactive, and FIG. 12(E) the timing (SAE) wherewith the sense amplifier 518 is either energized or deenergized, respectively.
A read operation will be carried out as follows. First, at time t=t0, both the row decoder energize signal (RAE) and the row address selection signal (RAdd) are driven to the xe2x80x9cHxe2x80x9d level (FIG. 12(A)), respectively. Then, the row decoder 524 is selected, and the output of the row decoder 524 is driven to the xe2x80x9cHxe2x80x9d level. When the row decoder 524 is selected, the word driver 522 is driven and the word line 512 (WL) is made active, that is, driven to the xe2x80x9cHxe2x80x9d level (time t=t0 (FIG. 12(C)). Thus a voltage is applied to the gates 504x and 506x of the two MOSFETs and the MOSFETs 504 and 506 are put in a conducting state. When the word line 512 (WL) becomes active, moreover, an xe2x80x9cHxe2x80x9d level signal is applied to the plate driver 526 connected to the word line 512. (The plate driver becomes in a control signal waiting state).
Next, at time t=t1, when the control signal (RS) goes high xe2x80x9cHxe2x80x9d (FIG. 12(B)), that is, when the control signal (RS) is applied to the plate driver 526, xe2x80x9cHxe2x80x9d level signal is output from the plate driver 526, and the plate line 510 (PL) becomes active (xe2x80x9cHxe2x80x9d level) (time t=t1 (FIG. 12(D))). Thereupon, the charge stored in the ferroelectric capacitor 500 begins to be distributed on the bit line 514. Similarly, the charge stored in the ferroelectric capacitor 502 begins to be distributed on the complementary bit line 516. Beginning at this time (t1), the potentials (BL and /BL) on the bit line 514 and the complementary bit line 516 change, respectively, in response to the distributed potentials (FIG. 12(F)).
Next, a sense amplifier drive signal (SAE) is applied, at time t=t2, for example, to the sense amplifier 518 to which the bit line 514 and complementary bit line 516 are connected (to drive to an xe2x80x9cHxe2x80x9d level (FIG. 12(E))). Thereby, the sense amplifier 518 latches the potential difference (xcex94V) between the potential (BL) appearing on the bit line 514 and the potential (/BL) appearing on the complementary bit line 516 to the potential difference with the power supply voltage level, transfers the difference to a data output circuit 528, and thus outputs the requisite data (FIG. 11).
After that, the ferroelectric capacitors 500 and 502 are restored by driving the control signal (RS) to the xe2x80x9cLxe2x80x9d level (time t=t3) (FIG. 12(B)).
Last of all, the word line 512 (WL) is made inactive by driving the row address selection signal (RAdd) to the xe2x80x9cLxe2x80x9d level, (t=t4)(FIG. 12(C)).
In general, the relative permittivity (dielectric constant) of a ferroelectric film is larger than the relative permittivity of a MOSFET oxidation film by roughly a two-digit factor. In the ferroelectric memory device described in the foregoing, moreover, the capacitances of the plurality of ferroelectric capacitors in the memory array are connected to the plate line 510, and the gate capacitances of the plurality of MOSFETs are connected to the word line 512. For that reason, despite the fact that the wiring lengths for both the plate line 510 and word line 512 are equivalent, the total load capacitance connected to the plate line 510 will end up being 30 to 50 times the total load capacitance connected to the word line 512. This results in the problem of the operating speed of the device becoming slow.
In a ferroelectric memory device having the configuration described in the foregoing, even if the size (specifically, the gate width) of the transistors configuring the plate driver 526 that imparts the requisite potential level to the plate line 510 is made large, parasitic resistance and parasitic capacitance will become large too in accordance therewith, so that one may still not expect high operating speeds to be realized in the device. Furthermore, the plate driver 526 in the ferroelectric memory device as shown in FIG. 11 is connected to the word line 512, and is provided on the opposite side from the word driver 522 that makes the word line 512 active, sandwiching the memory cell array 520 therebetween. Accordingly, if the size (specifically, the gate width) of the plate driver 526 is made large, the gate capacitance of the transistors configuring the plate driver 526 will also become large, wherefore the time required for activating the word line 512 (also called the rise time) will end up being increased.
That being so, the debut of a ferroelectric memory device wherewith the operation speed can be made even faster is anxiously awaited.
Ferroelectric memory devices have, prior to this, been proposed with the object of reducing load capacitances connected to plate lines. An example thereof is seen in the device disclosed in Reference 2 (Japanese Unexamined Patent Publication No. 7-220482/1995). Based on the art, a memory cell array is divided into a prescribed number of memory cell groups, and has, for each memory cell group, a divided cell plate line that connects commonly to one electrode of the ferroelectric capacitors in each memory cell. The divided cell plate line is connected to the cell plate line through a transmission transistor.
In the ferroelectric memory device disclosed in Reference 2 noted above, the load capacitances connected to the plate lines can be reduced, wherefore the plate line rise time can be shortened, and thus the operating speed of the device can be made even higher.
Nevertheless, even higher operating speeds are now demanded in ferroelectric memory devices.
An object of the present invention is to provide a ferroelectric memory device that facilitates achieving higher operating speeds by reducing the load capacitance placed on one plate line further than conventionally.
Another object of the present invention is to provide a ferroelectric memory device that facilitates achieving higher operating speeds by reducing the load capacitance placed on the word line.
Yet another object of the present invention is to provide a ferroelectric memory device the operating speed whereof can be made higher, using control signals from the outside.
Yet another object of the present invention is to provide a ferroelectric memory device wherein the load capacitances placed on the plate lines and sub-word lines are reduced further than conventionally.
Yet another object of the present invention is to provide a ferroelectric memory device the operating speed whereof can be made higher, putting the plate drivers in a condition of being non-connected to the word lines.
Yet another object of the present invention is to provide a ferroelectric memory device that makes it possible to reduce the device layout area while achieving high-speed operation.
And yet another object of the present invention is to provide an operation method for the ferroelectric memory devices described above.
Accordingly, as based on the ferroelectric memory device of the present invention, a plurality of memory cells, word line(s), plate line(s), and plate driver(s) are comprised, and the ferroelectric memory device has the structure described below. That is, the device has a word line to which a plurality of memory cells are connected, and those memory cells are divided between or into at least two memory cell groups. The memory cells configuring (or belonging to) one memory cell group are commonly connected to a plate line. The plate line is driven to either high level or low level by a plate driver provided for each memory cell group. Each of these plate drivers is connected to the word line, and at least one of the plate drivers is placed between memory cell groups that are provided adjacent to each other.
Based on this device, a plurality of memory cells connected to one word line are divided into a plurality of memory cell groups, and to each of those memory cell groups is connected one common plate line. In contrast to this, conventionally, a plurality of memory cells connected to one word line are all connected to one common plate line. Accordingly, in the present invention, because a common plate line is provided for each memory cell group, the number of memory cells connected to any one plate line is fewer than the unmber of conventional ones. That being so, the load capacitance placed on one plate line is made lower than the load capacitance of conventional one, wherefore the size of the transistors in the plate driver that activates or deactivates a plate line may be made smaller than the size of conventional ones. Accordingly, the parasitic resistance and parasitic capacitance of the transistors are reduced and, because of that, the plate line rise time can be shortened.
These plate drivers are connected to the word line, but at least one of these plate drivers is placed between two adjacent memory cell groups connected to the word line, and are connected to the word line. Be implementing this kind of structure, the load capacitance placed on the word line can be reduced below what it can be in a conventional structure wherein a plate driver of large capacitance is provided at the end of a word line opposite that where it is connected to the word driver. Thus the word line rise time can be shortened.
Accordingly, since the rise time in both the plate line(s) and word lines can be shortened, a ferroelectric memory device can be provide which exhibits a faster operating speed than conventionally.
In such a device as this, moreover, it is preferable that the plate driver be driven by word line activation, and by control signals from the outside. By drive here is meant the generation of a first level output. Hence to cause a plate driver to drive, in the present invention, is to have a word line activated (so that the potential on the word line goes to the xe2x80x9cHxe2x80x9d level), whereby an xe2x80x9cHxe2x80x9d level (first level) signal is input to the plate driver connected to the word line, and to have an xe2x80x9cHxe2x80x9d level signal input as a control signal from the outside, whereupon an xe2x80x9cHxe2x80x9d level signal is output from the plate driver as a first level signal.
According to this configuration, when the potential on a plate line is intended to be driven to the xe2x80x9cLxe2x80x9d level, the plate line can be driven to the xe2x80x9cLxe2x80x9d level in a short time by a control signal from the outside.
Preferably, moreover, that control signal from the outside may be made a row address selection signal or a column address selection signal. With such a configuration as this, the plate driver for a plate line connected to a selected memory cell group can be turned off by an address selection signal. Accordingly, the load required in turning a plate driver off can be made smaller than the load required in conventional one, wherefore the operating speed of the device can be made higher. The shortening of the time for turning the plate driver off, in specific terms, is associated with shortening the pre-charge time and cycle time until the next operation.
In another example configuration of the ferroelectric memory device of the present invention, the ferroelectric memory device has memory cell groups each configured by a plurality of memory cells, and the pluralities of memory cells are each connected to a plate line and a sub-word line that are common to each memory cell group. The common plate lines and the common sub-word lines are activated or deactivated by plate drivers and sub-word drivers connected respectively to each of the memory cell groups. The plate drivers are connected to sub-word lines, and the sub-word drivers are connected respectively to a main word line.
Based on a device structured in this way, a plate line and sub-word line are provided for each memory cell group. The number of memory cells connected to one plate line or sub-word line is fewer than conventionally, wherefore the wiring length for the plate lines and sub-word lines is shorter than for conventional word lines. For this reason, the load capacitance placed on each plate line and sub-word line becomes smaller than conventionally. As a consequence, the gate width of the transistor(s) in a plate driver that activates or deactivates one plate line, and the gate width of the transistor(s) in a sub-word driver that drives one sub-word line, may be smaller than conventionally.
When the output of a row decoder is driven to the xe2x80x9cHxe2x80x9d level by a row decoder energizing signal and a row address selection signal, the main word line to which the sub-word line is connected is activated (goes to the xe2x80x9cHxe2x80x9d level), but a sub-word driver to be driven can be selected from among a plurality of sub-word drivers connected to that main word line by a column address selection signal. Accordingly, power consumption can be reduced because only the desired sub-word driver is driven.
The sub-word line connected to the sub-word driver is shorter than a conventional word line, moreover, and the number of memory cells connected to the sub-word line is fewer than the number of memory cells connected to a conventional word line, wherefore the sub-word line rise time can be shortened.
Also, since a plate line is provided for each memory cell group, the number of memory cells connected to one plate line is fewer than conventionally. Accordingly, the load capacitance placed on the plate lines is far smaller than conventionally. The gate width of the transistors in the plate drivers that drive the plate lines can be made smaller, moreover, so the parasitic resistance and parasitic capacitance of the transistors can be reduced. Hence the plate line rise time can be shortened.
Accordingly, a ferroelectric memory device can be provided that has an operating speed which is faster than conventionally. In addition, the memory cells driven can be limited by using a column address selection signal to select the sub-word driver to drive, wherefore power consumption can be reduced.
In a device having such a configuration as this, moreover, it is preferable that the sub-word drivers noted above be driven by having an xe2x80x9cHxe2x80x9d level signal output from the row decoder by a row decoder energizing signal and a row address selection signal, and then have the xe2x80x9cHxe2x80x9d level output on the main word line activated by those signals and a column address selection signal applied thereto.
Thus, first, when an xe2x80x9cHxe2x80x9d level signal is output from the row decoder by the row decoder energizing signal and the row address selection signal, the main word line connected to the row decoder becomes active. Thereupon, all of the sub-word drivers connected to the main word line enter a wait state. By wait state is meant a state wherein driving can be done just as soon as a column address selection signal is applied. Next, the column address selection signal is applied to the sub-word driver to be driven. Thus it is possible to drive only the sub-word driver to which the column address selection signal is applied and to cause the output of an xe2x80x9cHxe2x80x9d level signal as the first level.
In the device described in the foregoing, furthermore, it is preferable that the plate drivers be driven by the activation of the sub-word lines, and by a column block selection signal that, after a row decoder energizing signal and a column address selection signal have been input to a column block selection circuit, is output from the column block selection circuit.
When a sub-word driver is driven (that is, when an xe2x80x9cHxe2x80x9d level signal is output from a sub-word driver), the sub-word line connected to the sub-word driver becomes active (its level goes to xe2x80x9cHxe2x80x9d). Thereupon, the plate driver connected to the sub-word line enters a wait state. Also, the row decoder energizing signal and column address selection signal are connected to the column block selection circuit. The column block selection circuit corresponds to the memory cell group(s), and is provided by being connected to the plate drivers. By applying the two signals mentioned above (i.e. the row decoder energizing signal and the column address selection signal) to the column block selection circuit, a column block selection signal is applied to a plate driver. Thus the plate driver is driven, and an xe2x80x9cHxe2x80x9d level output is generated as the first level. As a result, the plate line connected to the plate driver becomes active.
Accordingly, in this device, the sub-word drivers and plate drivers are finally controlled by the column address selection signals. That being so, each plate driver is controlled to turn on or off by a column address selection signal, wherefore the drive time can be shortened more than conventionally.
In another example configuration of the ferroelectric memory device of the present invention, the ferroelectric memory device has memory cell groups configured by pluralities of memory cells, and each of the pluralities of memory cells is connected to a common plate line and a common word line. These plate and word lines are respectively activated or deactivated by plate drivers and word drivers. The word drivers are driven when an xe2x80x9cHxe2x80x9d level signal is output from a row decoder, and the plate drivers are driven when an xe2x80x9cHxe2x80x9d level signal is output from a row decoder and a control signal from the outside is applied.
To the word lines in this device are not connected plate drivers. Thus the load capacitance placed on a word line will decline by the measure of the plate driver, wherefore the word line rise time and fall time can be shortened. As a consequence, the device can be made to operate at high speed.
Also, since the plate drivers and word lines are not connected, no redundant wiring is provided, and connections are easy to make.
In this device, it is preferable that the row decoder be selected by a row address selection signal and a row address energizing signal. By selection here is meant the selection and driving of a desired row decoder from among the row decoders provided for each of the rows, and causing the output of an xe2x80x9cHxe2x80x9d level signal as a first level signal.
It is also preferable that the control signal from the outside be made either a row address selection signal or a column address selection signal.
It is also preferable, in this device, that each plate driver be connected via a separate wired line to a wired line placed between a row decoder and a word driver.
By effecting such a configuration as this, it becomes possible to put a plate driver in a wait state by selecting and driving a row decoder. Measures are also effected so that a control signal from the outside is also applied to this plate driver. When that is done, by inputting the control signal, the plate driver in the wait state can be driven, and a first level output can be produced on the plate line.
In the device described in the foregoing, moreover, when a structure that contains a memory cell group, plate line, word line, plate driver, and word driver is called a block, a plurality of blocks are aligned in one queue in a direction perpendicular to the word lines or plate lines. When this is done, care is taken not to deploy the plate drivers and word drivers of adjacent blocks on the same side relative to the blocks.
Thus the pitch of the word drivers or plate drivers on one side relative to the blocks can be doubled and, accordingly, layout design can be done easily.
In another example configuration of the ferroelectric memory device of the present invention, the ferroelectric memory device has two memory cell groups configured by pluralities of memory cells, and these pluralities of memory cells are each connected to a common plate line and a common word line. The word line is made active or inactive by a word driver provided for each memory cell group. The two plate lines are respectively connected to a common plate driver. Either one or both of the plate lines are made active or inactive by the plate driver. The word driver is caused to be driven when an xe2x80x9cHxe2x80x9d level signal is output from a row decoder connected to the word driver. The plate driver is caused to be driven by the activation of one or both of the word lines and a control signal from the outside. That is, the plate driver is driven by the activation of one of the word lines and a control signal, and the plate line connected to the memory cells in the memory cell group on the side of the word line that became active becomes active. When both of the word lines become active and a control signal is input to this plate driver, the plate driver is driven, and both plate lines are made active.
Thus, in this device configuration, a common plate driver is provided for two memory cell groups, wherefore the number of transistors is fewer, and the wiring for applying the control signals is common also. Hence the layout area can be made smaller.
It is preferable that the plate driver such as described above have the configuration described below, for example.
First, the plate driver comprises two MOSFETs, each having a source common thereto, and the source is connected either to the row address selection signal or the column address selection signal. The gate of one of the two MOSFETs, furthermore, is connected to a common word line to one of the memory cell groups, and the drain thereof is connected to a common plate line to one of the memory cell groups. The gate of the other of the two MOSFETs is connected to a common plate line to the other memory cell group.
Furthermore, in a ferroelectric memory device having memory cell groups configured by pluralities of memory cells, wherein the pluralities of memory cells are each connected to a common plate line and a common sub-word line, the common plate lines and common sub-word lines are made active or inactive by a plate driver and a sub-word driver provided for each memory cell group, respectively, the plate drivers are connected to the sub-word lines, the sub-word drivers are connected to main word lines, and the main word lines are connected to row decoders, the operating process steps described below in (1) to (4) are negotiated in performing data read-out operations.
(1) A step for causing a row decoder to be selectively driven by inputting to the row decoder a row decoder energizing signal and a row address selection signal.
(2) A step for putting a sub-word driver in a wait state by inputting a first level (here being an xe2x80x9cHxe2x80x9d level) output to the main word line from the row decoder by selecting and driving the row decoder, and making the main word line active.
(3) A step for making a sub-word line active by causing an xe2x80x9cHxe2x80x9d level signal to be output from a sub-word driver to the sub-word line, by applying a column address selection signal to a sub-word driver that is in a wait state.
(4) A step for making a plate line active by inputting a row decoder energizing signal and a column address selection signal to a column block selection circuit and thereby inputting the column block selection signal output from the column block selection circuit to a waiting plate driver so as to cause an xe2x80x9cHxe2x80x9d level signal to be output from the plate driver to the plate line.
Thus it is possible to control the drive (on or off) of the plate drivers by column address selection signals, and therefore to shorten the operating time.
Furthermore, in operating a ferroelectric memory device configured such that it has memory cell groups configured by pluralities of memory cells, and wherein the pluralities of memory cells are each connected to a common plate line and a common word line, those plate lines and word lines are connected respectively to plate drivers and word drivers, and control signals are applied to those plate drivers from the outside, the operating process steps noted in (i) to (iii) below should be comprised.
(i) A step for causing a row decoder to be selectively driven, and causing an xe2x80x9cHxe2x80x9d level signal to be output as a first level signal from the row decoder, by inputting to the row decoder a row decoder energizing signal and a row address selection signal.
(ii) A step for causing a word driver connected to a row decoder to drive, making a word line active, and putting a plate driver connected to the row decoder in a wait state, by the output of an xe2x80x9cHxe2x80x9d level signal from the row decoder.
(iii) A step for causing a plate driver to drive and making a plate line active by applying a control signal to the plate driver in a wait state.
Thus putting a plate driver in a wait state is controlled by the output of an xe2x80x9cHxe2x80x9d level signal from a row decoder. Specifically, the plate driver is controlled not with a word line being active but with an address selection signal. Accordingly, the load placed on the word line can be made smaller, and the plate driver can be caused to be driven without raising the voltage.